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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator february 2004 rev. 1.0.2 general description the XRT75L00 is a single-channel fully integrated line interface unit (liu) with jitter attenuator for e3/ ds3/sts-1 applications. it incorporates an independent receiver, transmitter and jitter attenuator in a single 52 pin tqfp package. the XRT75L00 can be configured to operate in either e3 (34.368 mhz), ds3 (44.736 mhz) or sts-1 (51.84 mhz) modes. the transmitter can be turned off (tri- stated) for redundancy support and for conserving power. the XRT75L00s differential receiver provides high noise interference margin and is able to receive the data over 1000 feet of cable or with up to 12 db of cable attenuation. the XRT75L00 incorporates an advanced crystal- less jitter attenuator that can be selected either in the transmit or receive path. the jitter attenuator performance meets the etsi tbr-24 and bellcore gr-499 specifications. the XRT75L00 provides both serial microprocessor interface as well as hardware mode for programming and control. the XRT75L00 supports local, remote and digital loop-backs. the XRT75L00 also contains an on- board pseudo random binary sequence (prbs) generator and detector with the ability to insert and detect single bit error. features receiver: on chip clock and data recovery circuit for high input jitter tolerance. meets e3/ds3/sts-1 jitter tolerance requirements. detects and clears los as per g.775. meets bellcore gr-499 core jitter transfer requirements. receiver monitor mode handles up to 20 db flat loss with 6 db cable attenuation. compliant with jitter transfer template outlined in itu g.751, g.752, g.755 and gr-499-core,1995 standards. meets etsi tbr 24 jitter transfer requirements. on chip b3zs/hdb3 encoder and decoder that can be either enabled or disabled. on-chip clock synthesizer provides the appropriate rate clock from a single 12.288 mhz clock. provides low jitter output clock. transmitter: compliant with bellcore gr-499, gr-253 and ansi t1.102 specification for transmit pulse tri-state transmit output capability for redundancy applications transmitter can be turned on or off. jitter attenuator: on chip advanced crystal-less jitter attenuator. jitter attenuator can be selected in receive or transmit paths. 16 or 32 bits selectable fifo size. meets the jitter and wander specifications described in t1.105.03b,etsi tbr-24, bellcore gr-253 and gr-499 standards. jitter attenuator can be disabled. control and diagnostics: 5 wire serial microprocessor interface for control and configuration. supports optional internal transmit driver monitoring. prbs error counter register to accumulate errors. hardware mode for control and configuration. supports local, remote and digital loop-backs. single 3.3 v 5% power supply. 5 v tolerant i/o. available in 52 pin tqfp. -40c to 85c industrial temperature range. applications e3/ds3 access equipment. dslams. digital cross connect systems. csu/dsu equipment. routers. fiber optic terminals.
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 2 transmit interface characteristics accepts either single-rail or dual-rail data from terminal equipment and generates a bipolar signal to the line. integrated pulse shaping circuit. built-in b3zs/hdb3 encoder (which can be disabled). accepts transmit clock with duty cycle of 30%-70%. generates pulses that comply with the itu-t g.703 pulse template for e3 applications. generates pulses that comply with the dsx-3 pulse template, as specified in bellcore gr-499 -core and ansi t1.102_1993. generates pulses that comply with the stsx-1 pulse template, as specified in bellcore gr-253-core. transmitter can be turned off in order to support redundancy designs. receive interface characteristics integrated adaptive receive equalization for optimal clock and data recovery. declares and clears the los defect per itu-t g.775 requirements for e3 and ds3 applications. meets jitter tolerance requirements, as specified in itu-t g.823_1993 for e3 applications. meets jitter tolerance requirements, as specified in bellcore gr-499-core for ds3 applications. declares loss of signal (los) and loss of lock (lol) alarms. built-in b3zs/hdb3 decoder (which can be disabled). f igure 1. b lock d iagram of the xrt 75l00 host/hw sts-1/ds3 e3 reqen rtip rring sr/dr xrt75l03 rlb rlos jatx/rx tpdata tndata txclk taos txlev txon note: serial processor interface input pins are shared by in "host" mode and redefined in the "hardware" mode. device monitor mtip mring dmo timing control ttip tring tx pulse shaping hdb3/ b3zs encoder rlol rxon rxclkinv rxclk rpos rneg/ lcv tx control jitter attenuator mux line driver llb invert remote loopback hdb3/ b3zs decoder mux agc/ equalizer peak detector los detector slicer jitter attenuator serial processor interface local loopback clock & data recovery clock synthesizer exclk/12m reset cs sclk int sdo sdi clk_out
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 3 recovered data can be muted while the los condition is declared. outputs either single-rail or dual-rail data to the terminal equipment. jitter attenuators the XRT75L00 includes a jitter attenuator that meets the jitter requirements specified in the etsi tbr-24, bellcore gr-499 and gr-253 standards. in addition, the jitter attenuator also meets the jitter and wander specifications described in the ansi t1.105.03b 1997, bellcore gr-253 and gr-499 standards. f igure 2. p in o ut of the XRT75L00 ordering information p art n umber p ackage o perating t emperature r ange XRT75L00iv 52 pin tqfp -40 c to +85 c clk_out rpos rneg (lcv) rxclk gnd refagnd rext refavdd vdd rlos rlol int (losmut) sdo (rxmon) txlev taos txavdd txon txagnd ja0 ja1 ja tx/rx sfm_en rxavdd rring rtip rxagnd XRT75L00 (top view) 40 41 42 43 44 45 46 47 48 49 50 51 52 26 25 24 23 22 21 20 19 18 17 16 15 14 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 dmo mtip mring jaagnd exclk/12m jaavdd txclk tpdata tndata dgnd ttip tring dvdd sclk (txclkinv) sdi (rxon) cs (rxclkinv) reqen sr/dr host/hw e3 sts1/ds3 rlb llb ict test reset
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 i table of contents general description............................................................................................................ .. 1 f eatures ............................................................................................................................... ...................................... 1 a pplications ............................................................................................................................... ................................ 1 t ransmit i nterface c haracteristics ....................................................................................................................... 2 r eceive i nterface c haracteristics ......................................................................................................................... 2 f igure 1. b lock d iagram of the xrt 75l00 ..................................................................................................................... ................ 2 j itter a ttenuators ............................................................................................................................... ..................... 3 f igure 2. p in o ut of the XRT75L00 ...................................................................................................................... ............................ 3 ordering information........................................................................................................... ..........3 t able of c ontents i pin descriptions (by function) .......................................................................................... 4 t ransmit i nterface ............................................................................................................................... ..................... 4 r eceive i nterface ............................................................................................................................... ....................... 6 c lock i nterface ............................................................................................................................... .......................... 8 o perating m ode s elec t.............................................................................................................................. .............. 9 c ontrol and a larm i nterface ............................................................................................................................... ... 9 m icroprocessor s erial interface - (host mode)......................................................................................... 11 ............................................................................................................................... .................................................... 13 j itter a ttenuator interface ............................................................................................................................... ... 13 a nalog p ower and g round ............................................................................................................................... ..... 14 d igital p ower and g round ............................................................................................................................... ..... 14 1.0 electrical characteristics .............................................................................................. ......15 t able 1: a bsolute m aximum r atings ............................................................................................................................... ................ 15 t able 2: dc e lectrical c haracteristics :.............................................................................................................................. ......... 15 2.0 timing characteristics .................................................................................................. ............16 f igure 3. t ypical interface between terminal equipment and the XRT75L00 ( dual - rail data ) ................................................. 16 f igure 4. t ransmitter t erminal i nput t iming ............................................................................................................................... .. 16 f igure 5. r eceiver d ata output and code violation timing .......................................................................................................... 17 f igure 6. t ransmit p ulse a mplitude test circuit for e3, ds3 and sts-1 r ates ....................................................................... 17 3.0 line side characteristics: .............................................................................................. ..........18 3.1 e3 line side parameters: ................................................................................................ ...................... 18 f igure 7. p ulse m ask for e3 (34.368 mbits / s ) interface as per itu - t g.703 ............................................................................... 18 t able 3: e3 t ransmitter and receiver line side specifications (t a = 250c and vdd = 3.3 v 5%) .......................................... 18 f igure 8. b ellcore gr-253 core t ransmit o utput p ulse t emplate for sonet sts-1 a pplications ................................... 19 t able 4: sts-1 p ulse m ask e quations ............................................................................................................................... ............ 19 t able 5: sts-1 t ransmitter and r eceiver l ine s ide s pecifications (ta = 250c and vdd =3.3v 5%)................................... 20 f igure 9. t ransmit o uput p ulse t emplate for ds3 as per b ellcore gr-499 ........................................................................... 20 t able 6: ds3 p ulse m ask e quations ............................................................................................................................... ................ 21 t able 7: ds3 t ransmitter and r eceiver l ine s ide s pecifications (t a = 250c and vdd = 3.3v 5%) ...................................... 21 f igure 10. m icroprocessor s erial i nterface s tructure ............................................................................................................ 22 f igure 11. t iming d iagram for the m icroprocessor s erial i nterface ....................................................................................... 22 t able 8: m icroprocessor s erial i nterface t imings ( ta = 250c, vdd=3.3v 5% and load = 10 p f) ........................................ 23 4.0 the transmitter section: ............................................................................................... ..........24 4.1 transmit clock: ......................................................................................................... .............................. 24 4.2 b3zs/hdb3 encoder: ...................................................................................................... ........................... 24 4.2.1 b3zs encoding: ......................................................................................................... ............................................. 24 f igure 12. s ingle -r ail or nrz d ata f ormat (e ncoder and d ecoder are e nabled ) .................................................................. 24 f igure 13. d ual -r ail d ata f ormat ( encoder and decoder are disabled ).................................................................................... 24 4.2.2 hdb3 encoding:......................................................................................................... ............................................. 25 f igure 14. b3zs e ncoding f ormat ............................................................................................................................... .................. 25 f igure 15. hdb3 e ncoding f ormat ............................................................................................................................... .................. 25 4.3 transmit pulse shaper: .................................................................................................. ...................... 26 4.3.1 guidelines for using transmit build out circuit: ....................................................................... .......... 26 4.3.2 interfacing to the line:............................................................................................... ..................................... 26 4.4 transmit drive monitor: ................................................................................................. ...................... 26 4.5 transmitter section on/off: ............................................................................................. ................. 27 f igure 16. t ransmit d river m onitor set - up ............................................................................................................................... .... 27 5.0 the receiver section .................................................................................................... ..............28
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 ii 5.1 agc/equalizer ........................................................................................................... ................................ 28 5.1.1 interference tolerance................................................................................................. ................................. 28 f igure 17. i nterference m argin t est s et up for ds3/sts-1 ...................................................................................................... 29 f igure 18. i nterference m argin t est s et up for e3. ................................................................................................................... 29 t able 9: i nterference m argin t est r esults ............................................................................................................................... .. 29 5.2 clock and data recovery: ................................................................................................ .................. 30 5.3 b3zs/hdb3 decoder: ...................................................................................................... .......................... 30 5.4 los (loss of signal) detector: .......................................................................................... ............... 30 5.4.1 ds3/sts-1 los condition: ............................................................................................... ..................................... 30 d isabling alos/dlos d etector :........................................................................................................................... 30 5.4.2 e3 los condition:...................................................................................................... ............................................ 30 t able 10: t he alos (a nalog los) d eclaration and c learance t hresholds for a given setting of reqen (ds3 and sts-1 a p - plications ).............................................................................................................................. ............................................ 30 f igure 19. l oss o f s ignal d efinition for e3 as per itu-t g.775 ................................................................................................ 31 f igure 20. l oss of s ignal d efinition for e3 as per itu-t g.775................................................................................................. 31 5.4.2.1 m uting the r ecovered d ata with los condition : ......................................................................................... 32 6.0 jitter: ................................................................................................................. ............................... 33 6.1 jitter tolerance - receiver: ............................................................................................ .................. 33 6.1.1 ds3/sts-1 jitter tolerance requirements:............................................................................... ................ 33 f igure 21. j itter t olerance m easurements ............................................................................................................................... ... 33 6.1.2 e3 jitter tolerance requirements:...................................................................................... ....................... 34 f igure 22. i nput j itter t olerance f or ds3/sts-1 ..................................................................................................................... .34 f igure 23. i nput j itter t olerance for e3 ............................................................................................................................ ........ 34 6.2 jitter transfer - receiver/transmitter: ................................................................................. ..... 35 6.3 jitter generation: ...................................................................................................... ............................ 35 6.4 jitter attenuator: ...................................................................................................... ........................... 35 t able 11: j itter a mplitude versus m odulation f requency (j itter t olerance ) ......................................................................... 35 t able 12: j itter t ransfer s pecifications ............................................................................................................................... ....... 35 t able 13: j itter t ransfer p ass m asks ............................................................................................................................... ............ 36 f igure 24. j itter t ransfer r equirements and j itter a ttenuator p erformance ...................................................................... 36 7.0 serial host interface: .................................................................................................. ............. 37 t able 14: f unctions of shared pins ............................................................................................................................... ................. 37 t able 15: r egister m ap and b it n ames ............................................................................................................................... ............ 37 t able 16: r egister m ap d escription ............................................................................................................................... ............... 39 t able 17: r egister m ap d escription - g lobal ............................................................................................................................... 43 8.0 diagnostic features: .................................................................................................... ............. 44 8.1 prbs generator and detector: ............................................................................................ ............ 44 8.2 loopbacks: .............................................................................................................. .................................. 44 8.2.1 analog loopback:....................................................................................................... ........................................ 44 f igure 25. prbs mode ................................................................................................................ ................................................... 44 8.2.2 digital loopback:...................................................................................................... .......................................... 45 f igure 26. a nalog l oopback ............................................................................................................................... ............................ 45 f igure 27. d igital l oopback ............................................................................................................................... ............................. 45 8.2.3 remote loopback:....................................................................................................... ........................................ 46 8.3 transmit all ones (taos): ............................................................................................... ..................... 46 f igure 28. r emote l oopback ............................................................................................................................... ............................ 46 f igure 29. t ransmit a ll o nes (taos) ........................................................................................................................ .................... 46 o rdering i nformation ............................................................................................................................... .............. 47 package dimensions ............................................................................................................. 47 r evision h istory ............................................................................................................................... ....................... 48
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 4 pin descriptions ( by function ) transmit interface p in #s ignal n ame t ype d escription 4txon i transmitter on input setting this input pin "high" turns on the transmitter. n otes : 1. even when the XRT75L00 is configured in host mode, this pin still controls the ttip and tring outputs 2. when the transmitter is turned off either in host or hardware mode,the ttip and tring outputs are tri-stated. 3. this pin is internally pulled down 46 txclk i transmit clock input for tpdata and tndata the frequency accuracy of this input clock must be of nominal bit rate 20 ppm. the duty cycle can be 30%-70%. the XRT75L00 samples the tpdata and tndata pins on the falling or rising edge of txclk signal based on the status of txclkinv pin (in hardware mode) or the status of the bit in the channel register (in host mode). 26 txclkinv/ sclk i transmit clock invert or serial clock input: function of this depends on whether the XRT75L00 is configured to operate in hardware mode or host mode. in hardware mode, setting this input pin high configures the transmitter to sample the tpdata and tndata data on the rising edge of the txclk. n ote : if the XRT75L00 is configured in host mode, this pin functions as sclk input pin (please refer to the pin description for microprocessor interface). 48 tndata i transmit negative data input if the XRT75L00 is configured in dual-rail mode, this pin is sampled on the fall- ing or rising edge of txclk based on the status of the tclkinv pin (in hardware mode) or the status of the control bit in the channel register (in host mode). n otes : 1. this input pin is ignored and should be tied to gnd if the transmitter section is configured to accept single-rail data from the terminal equipment. 47 tpdata i transmit positive data input the XRT75L00 samples this pin on the falling or rising edge of txclk based on the status of the tclkinv pin (in hardware mode) or the status of the control bit in the channel register (in host mode). 50 ttip o transmit ttip output the XRT75L00 uses this pin along with tring to transmit a bipolar signal to the line using a 1:1 transformer.
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 5 51 tring o transmit ring output the XRT75L00 uses this pin along with ttip to transmit a bipolar signal to the line using a 1:1 transformer. 1txlev i transmit line build-out enable/disable select this input pin is used to enable or disable the transmit line build-out circuit. setting this pin to "high" disables the line build-out circuit. in this mode, par- tially-shaped pulses are output onto the line via the ttip and tring output pins. setting this pin to "low" enables the line build-out circuit. in this mode, shaped pulses are output onto the line via the ttipand tring output pins. to comply with the isolated dsx-3/stsx-1 pulse template requirements per bellcore gr-499-core or bellcore gr-253-core: 1. set this pin to "1" if the cable length between the cross-connect and the transmit output is greater than 225 feet. 2. set this pin to "0" if the cable length between the cross-connect and the transmit output is less than 225 feet. this pin is active only if the following two conditions are true: a. the XRT75L00 is configured to operate in either the ds3 or sonet sts-1 modes. b. the XRT75L00 is configured to operate in the hardware mode. n otes : 1. this pin is internally pulled down. 2. if the XRT75L00 is configured in host mode, this pin may be tied to gnd. transmit interface p in #s ignal n ame t ype d escription
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 6 receive interface p in #s ignal n ame t ype d escription 25 rxon/ sdi i receiver turn on input or serial data input: function of this pin depends on whether the XRT75L00 is configured to operate in hardware mode or host mode. in hardware mode, setting this input pin high turns on and enables the receiver.. n otes : 1. if the XRT75L00 is configured in host mode, this pin functions as sdi input pin (please refer to the pin description for microprocessor interface) 2. this pin is internally pulled down. 23 reqen i receive equalization enable input setting this input pin "high" enables the internal receive equalizer. setting this pin "low" disables the internal receive equalizer. n otes : 1. this input pin is ignored and may be connected to gnd if the XRT75L00 is operating in the host mode 2. this pin is internally pulled down. 36 rxclk o receive clock output the recovered clock signal from the incoming line signal is output through this pin.by default, the receiver section outputs data via rpos and rneg pins on the rising edge of this clock signal. configure the receiver section to update data on the rpos and rneg pins on the falling edge of rxclk by doing the following: a) operating in hardware mode , pull the rxclkinv pin to high. b) operating in host mode , write a 1 to rxclkinv bit field within the receive control register. 24 rxclkinv/ cs i rxclk invert or chip select : function of this pin depends on whether the XRT75L00 is configured to operate in hardware mode or host mode. in hardware mode, setting this input pin high configures the receiver sec- tion to invert the rxclk output signals and outputs the recovered data via rpos and rneg on the falling edge of rxclk. n ote : if the XRT75L00 is configured in host mode, this pin functions as cs input pin (please refer to the pin description for microprocessor interface). 38 rpos o receive positive data output this output pin pulses high" whenever the XRT75L00 has received a positive polarity pulse in the incoming line signal at the rtip/rring inputs.
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 7 37 rneg/lcv o receive negative data output/line code violation indicator function of these pins depends on whether the XRT75L00 is configured in single rail or dual rail mode. if the XRT75L00 is configured in dual rail mode, a negative pulse is output through rneg. in hardware mode: tie the pin sr/dr (pin 22) high to configure the XRT75L00 in single rail mode and tie low to configure in dual rail mode. in host mode: XRT75L00 can be configured in single rail or dual rail by set- ting or clearing the bit in the block control register. line code violation indicator if the XRT75L00 is configured in single rail mode then: whenever the receiver section detects a line code violation, it pulses this output pin high. this output pin remains low at all other times. it is advisable to sample this output pin using the rxclk output signal. 11 rring i receive ring input this input pin along with rtip is used to receive the bipolar line signal from the remote ds3/e3/sts-1 terminal. 12 rtip i receive tip input this input pin along with rrng is used to receive the bipolar line signal from the remote ds3/e3/sts-1 terminal. 27 rxmon/ sdo i receive monitoring mode or serial data output: in hardware mode, when this pin is tied high XRT75L00 configures into mon- itoring channel. in the monitoring mode, the receiver is capable of monitoring the signals with 20 db flat loss plus 6 db cable attenuation. this allows to moni- tor very weak signal before declaring los. in host mode, XRT75L00 can be configured to be a monitoring channel by setting the bits in the receive control register. n ote : if the XRT75L00 is configured in host mode, this pin functions as sdo pin (please refer to the pin description for the microprocessor interface). receive interface p in #s ignal n ame t ype d escription
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 8 clock interface p in #s ignal n ame t ype d escription 44 exclk/12m i clock input (34.368 mhz or 44.736 mhz or 51.84 mhz 20 ppm): based on the mode selected, provide the appropriate reference clock signal. if the XRT75L00 is configured for single frequency mode with the sfm_en tied high, then provide a 12.288 mhz 20 ppm clock and depending on the mode, the correct frequency is generated internally by the clock synthesizer.. 9sfm_en i single frequency enable: tie this pin high to select the single frequency mode. when enabled, a single frequency clock, 12.288 mhz is input through the exclk input pin and the inter- nal clock synthesizer generates the appropriate clock frequency. n ote : this pin is internally pulled down. 39 clk_out o clock out put: when the single frequency mode is selected, a low jitter clock will be out put. the frequency of this clock depends on whether the XRT75L00 is configured in e3 or ds3 or sts-1 mode.
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 9 operating mode select p in #s ignal n ame t ype d escription 21 host/(hw )i host/hardware mode select: tie this pin high to configure the XRT75L00 in host mode. tie this low to configure in hardware mode. when the XRT75L00 is configured in host mode, the states of many discrete input pins are ignored. n ote : this pin is internally pulled up. 20 e3 i e3 mode select input a "high" on this pin configures to operate in the e3 mode. a "low" on this pin configures to operate in either sts-1 or ds3 mode depend- ing on the setting on pin 19. n otes : 1. this pin is internally pulled down 2. this pin is ignored and may be tied to gnd if the XRT75L00 is configured to operate in host mode. 19 sts-1/ds3 i sts-1/ds3 select input a high on this pin configures to operate in sts-1 mode. a low on this pin configures to operate in ds3 mode. this pin is ignored if the e3 pin is set to high. n otes : 1. this pin is internally pulled down 2. this pin is ignored and may be tied to gnd if the XRT75L00 is configured to operate in host mode. 22 sr/dr i single-rail/dual-rail select: setting this high configures both the transmitter and receiver to operate in single-rail mode and also enables the b3zs/hdb3 encoder and decoder. in single-rail mode, transmit input at tndata should be grounded. setting this low configures both the transmitter and receiver to operate in dual-rail mode and disables the b3zs/hdb3 encoder and decoder. n ote : this pin is internally pulled down. control and alarm interface 42 mring i monitor ring input the bipolar line output signal from tring is connected to this pin via a 270 w resistor to check for line driver failure. n ote : this pin is internally pulled down. 41 mtip i monitor tip input the bipolar line output signal from ttip is connected to this pin via a 270-ohm resistor to check for line driver failure. n ote : this pin is internally pulled down. 40 dmo o drive monitor output if mtip and mring has no transition pulse for 128 32 txclk cycles, dmo goes high to indictae the driver failure. dmo output stays high until the next ami signal is detected.
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 10 30 rlos o receive loss of signal output indicator this output pin toggles "high" if receiver has detected a loss of signal condi- tion in the incoming line signal. the criteria for declaring/clearing an los condition depends upon whether it is operating in the e3 or sts-1/ds3 mode and is described in section 2.04. 29 rlol o receive loss of lock output indicator: this output pin toggles "high" if the XRT75L00 has detected a loss of lock condition. lol (loss of lock) condition is declared if the recovered clock fre- quency deviates from the reference clock frequency (available at exclk input pin) by more than 0.5%. 33 rext **** external bias control resistor of 3.3 k w 1%. should be connected to refagnd via 3.3 k w resistor. 15 test i test mode: connect this pin high to configure the XRT75L00 in test mode. n ote : this pin is internally pulled down. 16 ict i in-circuit test input : setting this pin "low" causes all digital and analog outputs to go into a high- impedance state to allow for in-circuit testing. for normal operation, set this pin "high". n ote : this pin is internally pulled high". 2taos i transmit all ones select a high" on this pin causes the transmitter section to generate and transmit a continuous ami all 1s pattern onto the line. the frequency of this 1s pattern is determined by txclk. n otes : 1. this input pin is ignored if the XRT75L00 is operating in the host mode and should be tied to gnd. 2. analog loopback and remote loopback have priority over request. 3. this pin is internally pulled down. 28 losmut/ int i/o mute-upon-los enable input or interrupt ouput: in hardware mode, setting this pin high configures the XRT75L00 to mute the recovered data on the rpos and rneg whenever an los condition is declared. rpos and rneg outputs are pulled low. n ote : if the XRT75L00 is configured in host mode, this pin functions as int pin (please refer to the pin description for the microprocessor interface). control and alarm interface
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 11 17 llb i local loop-back this input pin along with rlb configures different loop-back modes. n ote : this input pin is ignored and may be connected to gnd if the XRT75L00 is operating in the host mode. 18 rlb i remote loop-back this input pin along with llb configures different loop-back modes. n ote : this input pin is ignored and should be connected to gnd if the XRT75L00 is operating in the host mode. microprocessor serial interface - (host mode) p in #s ignal n ame t ype d escription 24 cs /rxclkinv i microprocessor serial interface - chip select tie this low to enable the communication with serial microprocessor inter- face. n ote : if the XRT75L00 is configured in hardware mode,this pin functions as rxclkinv. 26 sclk/txclkinv i serial interface clock input the data on the sdi pin is sampled on the rising edge of this signal. addition- ally, during read operations the microprocessor serial interface updates the sdo output on the falling edge of this signal. n ote : if the XRT75L00 is configured in hardware mode, this pin functions as txclkinv. 25 sdi/rxon i serial data input: data is serially input through this pin. the input data is sampled on the rising edge of the sclk pin (pin 26). n otes : 1. this pin is internally pulled down 2. if the XRT75L00 is configured in hardware mode, this pin functions as rxon. 27 sdo/rxmon o serial data output: this pin serially outputs the contents of the specified command register during read operations. the data is updated on the falling edge of the sclk and this pin is tri-stated upon completion of data transfer. n ote : if the XRT75L00 is configured in hardware mode, this pin functions as rxmon. control and alarm interface rlb 0 0 loopback mode normal operation analog local llb 0 1 1 1 remote digital 0 1
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 12 14 reset i register reset: setting this input pin "low" causes the XRT75L00 to reset the contents of the command registers to their default settings and default operating configuration n ote : this pin is internally pulled up. 28 int/ losmut i/o interrupt output: this pin functions as interrupt output for serial interface. a transition to low indicates that an interrupt has been generated by the serial interface. the inter- rupt function can be disabled by setting the interrupt enable bit to 0 in the channel control register. n ote : if the XRT75L00 is in hardware mode, this pin functions as losmut. microprocessor serial interface - (host mode) p in #s ignal n ame t ype d escription
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 13 jitter attenuator interface p in #s ignal n ame t ype d escription 6 ja0 i disable jitter attenuator/fifo size select:: in hardware mode, this pin along with ja1 pin provides the following functions in the table below. n ote : this pin is internally pulled down. 7 ja1 i disable jitter attenuator/fifo size select: in hardware mode, this pin along with ja0 pin provides the functions in the table above. n ote : this pin is internally pulled down. 8 ja tx/rx i jitter attenuator select: in hardware mode setting this pin high selects the jitter attenuator in the transmit path and setting low selects in receive path. n ote : this pin is internally pulled down. ja0 0 0 operation 16 bit fifo 32 bit fifo ja1 0 1 1 1 disable jitter attenuator disable jitter attenuator 0 1
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 14 analog power and ground p in #s ignal n ame t ype d escription 3 txavdd **** transmitter analog vdd 3.3 v 5% 10 rxavdd **** receiver analog vdd 3.3 v 5% 32 refavdd **** reference analog vdd 3.3 v 5% 5 txagnd **** transmitter analog gnd 13 rxagnd **** receiver analog gnd 34 refagnd **** reference analog gnd 45 jaavdd **** jitter attenuator analog vdd 3.3 v 5% 43 jaagnd **** jitter attenuator analog gnd digital power and ground p in #s ignal n ame t ype d escription 31 dvdd **** vdd 3.3 v 5% receiver digital 35 dgnd **** gnd 52 dvdd **** vdd 3.3 v 5% transmitter digital 49 dgnd **** gnd
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 15 1.0 electrical characteristics n otes : 1. exposure to or operating near the min or max values for extended period may cause permanent failure and impair reliability of the device. 2. esd testing method is per mil-std-883d,m-3015.7 n otes : 1. not applicable for pins with pull-up or pull-down resistors. 2. the digital inputs and outputs are ttl 5v compliant. t able 1: a bsolute m aximum r atings symbol p arameter min max units comments v dd supply voltage -0.5 6.0 v note 1 v in input voltage at any pin -0.5 5+0.5 v note 1 i in input current at any pin 100 ma note 1 s temp storage temperature -65 150 0 c note 1 a temp ambient operating temperature -40 85 0 c linear airflow 0 ft./min thetaja thermal resistance 20 0 c/w linear air flow 0ft/min thetajc 6 0 c/w m levl exposure to moisture 5 level eia/jedec jesd22-a112-a esd esd rating 2000 v note 2 t able 2: dc e lectrical c haracteristics : symbol p arameter min . typ . max . units dv dd digital supply voltage 3.135 3.3 3.465 v av dd analog supply voltage 3.135 3.3 3.465 v i cc supply current (measured while transmitting and receiving all 1s) 75 150 225 ma p dd power dissipation 235 495 780 mw v il input low voltage 0.8 v v ih input high voltage 2.0 5.0 v v ol output low voltage, i out = - 4ma 0.4 v v oh output high voltage, i out = 4 ma 2.4 v i l input leakage current 1 10 m a c i input capacitance 10 pf c l load capacitance 10 pf
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 16 2.0 timing characteristics f igure 3. t ypical interface between terminal equipment and the XRT75L00 ( dual - rail data ) f igure 4. t ransmitter t erminal i nput t iming symbol parameter min typ max units txclk duty cycle e3 ds3 sts-1 30 50 34.368 44.736 51.84 70 % mhz mhz mhz t rtx txclk rise time (10% to 90%) 4 ns t ftx txclk fall time (10% to 90%) 4 ns t tsu tpdata/tndata to txclk falling set up time 3 ns t tho tpdata/tndata to txclk falling hold time 3 ns t tdy ttip/tring to txclk rising propagation delay time 8 ns terminal equipment (e3/ds3 or sts-1 framer) exar e3/ds3/sts-1 liu transmit logic block txpos txneg txlineclk tpdata tndata txclk tpdata or tndata ttip or tring txclk t tsu t tho t rtx t ftx t tdy
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 17 f igure 5. r eceiver d ata output and code violation timing symbol parameter min typ max units rxclk duty cycle e3 ds3 sts-1 45 50 34.368 44.736 51.84 55 % mhz mhz mhz t rrx rxclk rise time (10% o 90%) 2 4 ns t frx rxclk falling time (10% to 90%) 2 4 ns t co rxclk to rpos/rneg delay time 4 ns t lcvo rxclk to rising edge of lcv output delay 2.5 ns f igure 6. t ransmit p ulse a mplitude test circuit for e3, ds3 and sts-1 r ates rclk t rrx t frx rpos or rneg lcv t lcvo t co 3.3k w + 1% ttip tring 1:1 r3 75 w txpos txneg txlineclk tpdata tndata txclk rext 37.4 w + 1% 37.4 w +1% r1 r2 refagnd
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 18 3.0 line side characteristics: 3.1 e3 line side parameters: the XRT75L00 meets the pulse shape specified in itu-t g.703 for 34.368 mbits/s operation at the secondary of the transformer. the pulse mask as specified in itu-t g.703 for 34.368 mbits/s is shown in figure 7. f igure 7. p ulse m ask for e3 (34.368 mbits / s ) interface as per itu - t g.703 t able 3: e3 t ransmitter and receiver line side specifications (t a = 25 0 c and vdd = 3.3 v 5%) parameter min typ max units t ransmitter line side output characteristics transmit output pulse amplitude (measured at secondary of the transformer) 0.90 1.00 1.10 v pk transmit output pulse amplitude ratio 0.95 1.00 1.05 transmit output pulse width 12.5 14.55 16.5 ns intrinsic jitter 0.02 0.05 ui pp r eceiver line side input characteristics receiver sensitivity (length of cable) 1200 feet interference margin -20 -15 db jitter tolerance @ jitter frequency 800khz 0.15 0.28 ui pp signal level to declare loss of signal -35 db signal level to clear loss of signal -15 db occurence of los to los declaration time 10 255 ui termination of los to los clearance time 10 255 ui 0% 50% v = 100% 14.55ns nominal pulse 12.1ns (14.55 - 2.45) 17 ns (14.55 + 2.45) 8.65 ns 10% 10% 20%
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 19 f igure 8. b ellcore gr-253 core t ransmit o utput p ulse t emplate for sonet sts-1 a pplications t able 4: sts-1 p ulse m ask e quations t ime in u nit i ntervals n ormalized a mplitude lower curve -0.85 < t < -0.38 - 0.03 -0.38 < t < 0.36 0.36 < t < 1.4 - 0.03 upper curve -0.85 < t < -0.68 0.03 -0.68 < t < 0.26 0.26 < t < 1.4 0.1 + 0.61 x e -2.4[t-0.26] sts-1 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 -0.8 - 0. 7 -0.6 - 0.5 - 0. 4 - 0.3 - 0.2 -0.1 0 0.1 0. 2 0.3 0. 4 0.5 0. 6 0. 7 0.8 0. 9 1 1.1 1. 2 1.3 1. 4 time, in ui normalized amplitude lower curve upper curve 0.5 1 p 2 -- -1 t 0.18 ---------- ? ? 0.03 C + ? sin + 0.5 1 p 2 -- - 1 t 0.34 ---------- ? ? 0.03 ++ ? sin +
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 20 t able 5: sts-1 t ransmitter and r eceiver l ine s ide s pecifications (ta = 25 0 c and vdd =3.3v 5%) p arameter m in t yp m ax u nits t ransmitter line side output characteristics transmit output pulse amplitude (measured with txlev = 0) 0.65 0.75 0.90 v pk transmit output pulse amplitude (measured with txlev = 1) 0.90 1.00 1.10 v pk transmit output pulse width 8.6 9.65 10.6 ns transmit output pulse amplitude ratio 0.90 1.00 1.10 intrinsic jitter 0.02 0.05 ui pp r eceiver line side input characteristics receiver sensitivity (length of cable) 900 1100 feet jitter tolerance @ jitter frequency 400 khz 0.15 0.60 ui pp signal level to declare loss of signal refer to table 10 signal level to clear loss of signal refer to table 10 f igure 9. t ransmit o uput p ulse t emplate for ds3 as per b ellcore gr-499 ds3 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 - 0.9 - 0 .8 - 0.7 - 0.6 - 0.5 - 0.4 - 0. 3 - 0.2 - 0 .1 0 0. 1 0 . 2 0. 3 0.4 0. 5 0 . 6 0. 7 0 . 8 0. 9 1 1.1 1 . 2 1 . 3 1 . 4 time, in ui normalized amplitude lower curve upper curve
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 21 t able 6: ds3 p ulse m ask e quations t ime in u nit i ntervals n ormalized a mplitude lower curve -0.85 < t < -0.36 - 0.03 -0.36 < t < 0.36 0.36 < t < 1.4 - 0.03 upper curve -0.85 < t < -0.68 0.03 -0.68 < t < 0.36 0.36 < t < 1.4 0.08 + 0.407 x e -1.84[t-0.36] t able 7: ds3 t ransmitter and r eceiver l ine s ide s pecifications (t a = 25 0 c and vdd = 3.3v 5%) p arameter m in t yp m ax u nits t ransmitter line side output characteristics transmit output pulse amplitude (measured with txlev = 0) 0.65 0.75 0.85 v pk transmit output pulse amplitude (measured with txlev = 1) 0.90 1.00 1.10 v pk transmit output pulse width 10.10 11.18 12.28 ns transmit output pulse amplitude ratio 0.90 1.00 1.10 intrinsic jitter 0.02 0.05 ui pp r eceiver line side input characteristics receiver sensitivity (length of cable) 900 1100 feet jitter tolerance @ 400 khz (cat ii) 0.15 0.60 ui pp signal level to declare loss of signal refer to table 10 signal level to clear loss of signal refer to table 10 0.5 1 p 2 -- -1 t 0.18 ---------- ? ? 0.03 C + ? sin + 0.5 1 p 2 -- - 1 t 0.34 ---------- ? ? 0.03 ++ ? sin +
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 22 f igure 10. m icroprocessor s erial i nterface s tructure f igure 11. t iming d iagram for the m icroprocessor s erial i nterface d0 d1 d2 d7 d6 d5 d4 d3 high z sdo a0 d0 r/w d1 0 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 sdi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sclk cs high z sdi r/w a1 a0 cs sclk cs sclk sdi sdo d0 d1 d2 d7 t 21 t 22 t 23 t 24 t 26 t 27 t 28 t 29 t 30 t 31 t 32 hi-z hi-z t 25
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 23 t able 8: m icroprocessor s erial i nterface t imings ( t a = 25 0 c, v dd =3.3v 5% and load = 10 p f) s ymbol p arameter m in .t yp .m ax u nits t 21 cs low to rising edge of sclk 5 ns t 22 sdi to rising edge of sclk 5 ns t 23 sdi to rising edge of sclk hold time 5 ns t 24 sclk "low" time 25 ns t 25 sclk "high" time 25 ns t 26 sclk period 50 ns t 27 falling edge of sclk to rising edge of cs 0ns t 28 cs "inactive" time 50 ns t 29 falling edge of sclk to sdo valid time 20 ns t 30 falling edge of sclk to sdo invalid time 10 ns t 31 rising edge of cs to high z 10 ns t 32 rise/fall time of sdo output 5 ns
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 24 4.0 the transmitter section: the transmitter section accepts ttl/cmos level signals from the terminal equipment in the selectable data formats. in single-rail or un-encoded non-return-to-zero (nrz) input data via tpdata pin while the tndata pin must be grounded. the nrz or single-rail mode is selected when the sr/dr input pin is high (in hardware mode) or bit 0 of the control register is 1 (in host mode). figure 12 illustrates the single-rail or nrz format. in dual-rail mode, data is input via tpdata and tndata pins. tpdata contains positive data and tndata contains negative data. the sr/dr input pin = low (in hardware mode) or bit 0 of the control register = 0 (in host mode) enables the dual-rail mode. figure 13 illustrates the dual-rail data format. convert the cmos level b3zs or hdb3 encoded data into pulses with shapes that are compliant with the various industry standard pulse template requirements. figure 7, figure 8 and figure 9 illustrate the pulse template requirements. encode the un-encoded nrz data into either b3zs format (for ds3 or sts-1) or hdb3 format (for e3) and convert to pulses with shapes and width that are compliant with industry standard pulse template requirements. figure 7,figure 8 and figure 9 illustrate the pulse template requirements. 4.1 t ransmit c lock : the transmit clock applied via txclk pin, for the selected data rate (for e3 = 34.368 mhz, ds3 = 44.736 mhz or sts-1 = 51.84 mhz), is duty cycle corrected by the internal pll circuit to provide a 50% duty cycle clock to the pulse shaping circuit. this allows a 30% to 70% duty cycle transmit clock be supplied and thus eliminates the need to use an expensive oscillator. 4.2 b3zs/hdb3 e ncoder : when the single-rail (nrz) data format is selected, the encoder block encodes the data into either b3zs format (for either ds3 or sts-1) or hdb3 format (for e3). 4.2.1 b3zs encoding: f igure 12. s ingle -r ail or nrz d ata f ormat (e ncoder and d ecoder are e nabled ) f igure 13. d ual -r ail d ata f ormat ( encoder and decoder are disabled ) txclk tpdata data 1 1 0 txclk tpdata tndata data 1 1 0
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 25 an example of b3zs encoding is shown in figure 14. if the encoder detects an occurrence of three consecutive zeros in the data stream, it is replaced with either b0v or 00v, where b refers to bipolar pulse that is compliant with the alternating polarity requirement of the ami (alternate mark inversion) line code and v refers to a bipolar violation (e.g., a bipolar pulse that violates the ami line code). the substitution of b0v or 00v is made so that an odd number of bipolar pulses exist between any two consecutive violation (v) pulses. this avoids the introduction of dc component into the line signal. 4.2.2 hdb3 encoding: an example of the hdb3 encoding is shown in figure 15.if the hdb3 encoder detects an occurrence of four consecutive zeros in the data stream, then the four zeros are substituted with either 000v or b00v pattern. the substitution code is made in such a way that an odd number of bipolar (b) pulses exist between any consecutive v pulses. this avoids the introduction of dc component into the analog signal. n otes : 1. when dual-rail data format is selected, the b3zs/hdb3 encoder is automatically disabled. 2. in dual-rail format, the bipolar violations in the incoming data stream is converted to valid data pulses. 3. encoder and decoder is enabled only in single-rail mode. f igure 14. b3zs e ncoding f ormat f igure 15. hdb3 e ncoding f ormat 000 1 1 1 1 1 1 1 v b v 1 0 00 00 0 0 0 0 0 0 0 000 v bv 0 00 tclk line signal tpdata 0 0 000 1 1 1 1 1 1 1 v b v 1 0 00 00 0 0 0 0 0 0 0 0 00 v 0 0 00 tclk line signal tpdata
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 26 4.3 t ransmit p ulse s haper : the transmit pulse shaper converts the b3zs encoded digital pulses into a single analog alternate mark inversion (ami) pulse that meet the industry standard mask template requirements for sts-1 and ds3. see figure 8 and figure 9. for e3 mode, the pulse shaper converts the hdb3 encoded pulses into a single full amplitude square shaped pulse with very little slope. this is illustrated in figure 7. the pulse shaper block also consists of a transmit build out circuit, which can either be disabled or enabled by setting the txlev input pin high or low (in hardware mode) or setting the txlev bit to 1 or 0 in the control register (in host mode). for ds3/sts-1 rates, the transmit build out circuit is used to shape the transmit waveform that ensures that transmit pulse template requirements are met at the cross-connect system. the distance between the transmitter output and the cross-connect system can be between 0 to 450 feet. for e3 rate, since the output pulse template is measured at the secondary of the transformer and since there is no cross-connect system pulse template requirements, the transmit build out circuit is always disabled. 4.3.1 guidelines for using transmit build out circuit: if the distance between the transmitter and the dsx3 or stsx-1, cross-connect system, is less than 225 feet, enable the transmit build out circuit by setting the txlev input pin low (in hardware mode) or setting the txlev control bit to 0 (in host mode). if the distance between the transmitter and the dsx3 or stsx-1 is greater than 225 feet, disable the transmit build out circuit. 4.3.2 interfacing to the line: the differential line driver increases the transmit waveform to appropriate level and drives into the 75 w load as shown in figure 6. 4.4 transmit drive monitor: this feature is used for monitoring the transmit line for occurrence of fault conditions such as short circuit on the line or defective line driver.the device can also be configured for internal tranmit driver monitoring. to monitor the transmitter output of another chip, connect mtip pin to the ttip line via a 270 w resistor and mring pins to tring line via 270 w resistor as shown in figure 16
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 27 in order to configure the device for internal transmit driver monitoring, set the txmon bit to 1 in the transmit control register. when the mtip and mring are connected to the ttip and tring lines, the drive monitor circuit monitors the line for transitions. the dmo (drive monitor output) will be asserted low as long as the transitions on the line are detected via mtip and mring. if no transitions on the line are detected for 128 32 txclk periods, the dmo output toggles high and when the transitions are detected again, dmo toggles low. n ote : the drive monitor circuit is only for diagnostic purposes and does not have to be used to operate the transmitter. 4.5 transmitter section on/off: the transmitter section can be turned on or off. to turn on the transmitter in the hardware mode, pull txon pin high. in the host mode, write a 1 to the txon control bit and pull the txon pin high to turn on the transmitter. when the transmitter is turned off, the ttip and tring are tri-stated. n otes : 1. this feature provides support for redundancy. 2. if the XRT75L00 is configured in host mode, to permit a system designed for redundancy to quickly shut-off the defective line card and turn on the back-up line card, writing a 1 to the txon control bit transfers the control to txon pin. f igure 16. t ransmit d river m onitor set - up . 3.3k w + 1% ttip tring XRT75L00 1:1 r3 75 w txpos txneg txlineclk tpdata tndata txclk rext refagnd 37.4 w + 1% 37.4 w +1% r1 r2 mring mtip r5 270 w r4 270 w 3.3k w + 1% txpos txneg txlineclk tpdata tndata txclk rext refagnd mring mtip ttip tring r3 75 w 37.4 w + 1% 37.4 w +1% r1 r2 1:1
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 28 5.0 the receiver section this section describes the detailed operation of the various blocks in the receiver. the receiver recovers the ttl/cmos level data from the incoming bipolar b3zs or hdb3 encoded input pulses. 5.1 agc/equalizer the adaptive gain control circuit amplifies the incoming analog signal and compensates for the various flat losses and also for the loss at one-half symbol rate. the agc has a dynamic range of 30 db. the equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of up to 900 feet of coaxial cable (1300 feet for e3). the equalizer also boosts the high frequency content of the signal to reduce the inter-symbol interference (isi) so that, the slicer slices the signal at 50% of peak voltage to generate positive and negative data. the equalizer can either be in or out by setting the reqen pin high or low (in hardware mode) or setting the reqen control bit to 1 or 0 (in host mode). r ecommendations for e qualizer s ettings the equalizer has two gain settings to provide optimum equalization. in the case of normally shaped ds3/ sts-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable, the equalizer can be left in by setting the reqen pin to high (in hardware mode) or setting the reqen control bit to 1 (in host mode). however, for square-shaped pulses such as e3 or for ds3/sts-1 high pulses (that does not meet the pulse template requirements), it is recommended that the equalizer be left out for cable length less than 300 feet by setting the reqen pin low (in hardware mode) or by setting the reqen control bit to 0 (in host mode).this would help to prevent over-equalization of the signal and thus optimize the performance in terms of better jitter transfer characteristics. n ote : the results of extensive testing indicates that even when the equalizer was left in (reqen = high), regardless of the cable length, the integrity of the e3 signal was restored properly over 0 to 12 db cable loss at industrial temperature. the equalizer also contain an additional 20 db gain stage to provide the line monitoring capability of the resistively attenuated signals which may have 20db flat loss. this capability can be turned on by writing a 1 to the rxmon bits in the control register or by setting the rxmon pin (pin 27) high. 5.1.1 interference tolerance for e3 mode, itu-t g.703 recommendation specifies that the receiver be able to recover error-free clock and data in the presence of a sinusoidal interfering tone signal. for ds3 and sts-1 modes, the same recommendation is being used. figure 17 shows the configuration to test the interference margin for ds3/ sts1. figure 18 shows the set up for e3.
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 29 f igure 17. i nterference m argin t est s et up for ds3/sts-1 f igure 18. i nterference m argin t est s et up for e3. t able 9: i nterference m argin t est r esults m ode c able l ength (a ttenuation )i nterference t olerance e3 0 db -14 db 12 db -18 db ds3 0 feet -17 db 225 feet -16 db 450 feet -16 db sts-1 0 feet -16 db 225 feet -15 db 450 feet -15 db sine wave generator pattern generator 2 23 - 1 prbs m attenuator ds3 = 22.368 mhz sts-1 = 25.92 mhz s n cable simulator dut XRT75L00 test equipment noise generator pattern generator m attenuator 1 s n cable simulator dut XRT75L00 test equipment attenuator 2
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 30 5.2 clock and data recovery: the clock and data recovery circuit extracts the embedded clock, from the sliced digital data stream and provides the retimed data to the b3zs (hdb3) decoder. the clock recovery pll can be in one of the following two modes: t raining m ode : in the absence of input signals at rtip and rring pins, or when the frequency difference between the recovered line clock signal and the reference clock applied on the exclk input pin exceed 0.5%, the clock recovery unit enters into training mode and a loss of lock condition is declared by toggling rlol output pin high (in hardware mode) or setting the rlol bit to 1 in the control registers (in host mode). also, the clock output on the rxclk pin is the same as the reference clock applied on exclk pin. d ata /c lock r ecovery m ode : in the presence of input line signals on the rtip and rring input pins and when the frequency difference between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on the rxclk out pin is the recovered clock signal. 5.3 b3zs/hdb3 decoder: the decoder block takes the output from clock and data recovery block and decodes the b3zs (for ds3 or sts-1) or hdb3 (for e3) encoded line signal and detects any coding errors or excessive zeros in the data stream. whenever the input signal violates the b3zs or hdb3 coding sequence for bipolar violation or contains three (for b3zs) or four (for hdb3) or more consecutive zeros, an active high pulse is generated on the rlcv output pins to indicate line code violation. n ote : in single- rail (nrz) mode, the decoder is bypassed. 5.4 los (loss of signal) detector: 5.4.1 ds3/sts-1 los condition: a digital loss of signal (dlos) condition occurs when a string of 175 75 consecutive zeros occur on the line. when the dlos condition occurs, the dlos bit is set to 1 in the status control register. dlos condition is cleared when the detected average pulse density is greater than 33% for 175 75 pulses. analog loss of signal (alos) condition occurs when the amplitude of the incoming line signal is below the threshold as shown in the table 10.the status of the alos condition is reflected in the alos status control register. rlos is the logical or of the dlos and alos states. when the rlos condition occurs the rlos output pin is toggled high and the rlos bit is set to 1 in the status control register. d isabling alos/dlos d etector : for debugging purposes it is useful to disable the alos/dlos detector. writing a 1 to the alos and dlos bits disables the los detector on a per channel basis. 5.4.2 e3 los condition: if the level of incoming line signal drops below the threshold as described in the itu-t g.775 standard, the los condition is detected. loss of signal level is defined to be between 15 and 35 db below the normal level. if t able 10: t he alos (a nalog los) d eclaration and c learance t hresholds for a given setting of reqen (ds3 and sts-1 a pplications ) a pplication reqen s etting s ignal l evel to d eclare alos s ignal l evel to c lear alos ds3 1< 20mv > 90mv sts-1 1< 25mv > 115mv
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 31 the signal drops below 35 db for 175 75 consecutive pulse periods, los condition is declared. this is illustrated in figure 19. as defined in itu-t g.775, an los condition is also declared between 10 and 255 ui (or e3 bit periods) after the actual time the los condition has occurred. the los condition is cleared within 10 to 255 ui after restoration of the incoming line signal. figure 20 shows the los declaration and clearance conditions. f igure 19. l oss o f s ignal d efinition for e3 as per itu-t g.775 f igure 20. l oss of s ignal d efinition for e3 as per itu-t g.775. 0 db -12 db -15db -35db maximum cable loss for e3 los signal must be declared los signal must be cleared los signal may be cleared or declared actual occurrence of los condition line signal is restored time range for los declaration time range for los clearance g.775 compliance g.775 compliance 0 ui 10 ui 0 ui 10 ui 255 ui 255 ui rtip/ rring rlos output pin
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 32 5.4.2.1 muting the recovered data with los condition: when the los condition is declared, the clock recovery circuit locks into the reference clock applied to the exclk pin and output this clock on the rxclk output. the data on the rpos and rneg pins can be forced to zero by pulling the losmut pin high (in hardware mode) or by setting the losmut bits in the individual channel control register to 1 (in host mode). n ote : when the los condition is cleared, the recovered data is output on rpos and rneg pins.
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 33 6.0 jitter: there are three fundamental parameters that describe circuit performance relative to jitter: jitter tolerance (receiver) jitter transfer (receiver/transmitter) jitter generation 6.1 j itter t olerance - r eceiver : jitter tolerance is a measure of how well a clock and data recovery unit can successfully recover data in the presence of various forms of jitter. it is characterized by the amount of jitter required to produce a specified bit error rate. the tolerance depends on the frequency content of the jitter. jitter tolerance is measured as the jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error rate (ber). to measure the jitter tolerance as shown in figure 21, jitter is introduced by the sinusoidal modulation of the serial data bit sequence. input jitter tolerance requirements are specified in terms of compliance with jitter mask which is represented as a combination of points.each point corresponds to a minimum amplitude of sinusoidal jitter at a given jitter frequency. 6.1.1 ds3/sts-1 jitter tolerance requirements: bellcore gr-499 core, issue 1, december 1995 specifies the minimum requirement of jitter tolerance for category i and category ii. the jitter tolerance requirement for category ii is the most stringent. figure 22 shows the jitter tolerance curve as per gr-499 specification along with the measured performance for the device. f igure 21. j itter t olerance m easurements freq synthesizer freq synthesizer pattern generator pattern generator dut XRT75L00 dut XRT75L00 error detector error detector modulation freq. data clock
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 34 6.1.2 e3 jitter tolerance requirements: itu-t g.823 standard specifies that the clock and data recovery unit must be able to accommodate and tolerate jitter up to certain specified limits. figure 23 shows the tolerance curve and the actual measured data for the device. the figure 11 below shows the jitter amplitude versus the modulation frequency for various standards. f igure 22. i nput j itter t olerance f or ds3/sts-1 f igure 23. i nput j itter t olerance for e3 0.01 0.03 15 1.5 0.3 2 20 0.15 jitter amplitude (ui pp ) jitter frequency (khz) 10 5 0.3 100 0.1 gr-253 sts-1 gr-499 cat ii gr-499 cat i 64 41 XRT75L00 0.1 1.5 1 10 jitter amplitude (ui pp ) jitter frequency (khz) 800 itu-t g.823 64 10 0.3 XRT75L00
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 35 6.2 j itter t ransfer - r eceiver /t ransmitter : jitter transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input versus frequency. there are two distinct characteristics in jitter transfer: jitter gain (jitter peaking) defined as the highest ratio above 0 db; and jitter transfer bandwidth.the overall jitter transfer bandwidth is controller by a low bandwidth loop,which is part of the XRT75L00.. the jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often expressed in db. a negative db jitter transfer indicates the element removed jitter. a positive db jitter transfer indicates the element added jitter.a zero db jitter transfer indicates the element had no effect on jitter. table 12 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates. the XRT75L00 meets the above jitter specifications. 6.3 j itter g eneration : jitter generation is defined as the process whereby jitter appears at the output port of the digital equipment in the absence of applied input jitter. jitter generation is measured by sending jitter free data to the clock and data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. since this is essentially a noise measurement, it requires a definition of bandwidth to be meaningful. the bandwidth is set according to the data rate. in general, the jitter is measured over a band of frequencies. 6.4 jitter attenuator: an advanced crystal-less jitter attenuator is included in the XRT75L00. the jitter attenuator uses the internal reference clock. in host mode, by clearing or setting the jatx/rx bit in the control register selects the jitter attenuator either in the receive or transmit path. in hardware mode, jatx/rx pin selects the jitter attenuator in receive or transmit path. the fifo is either a 16-bit or 32-bit register. in host mode, the bits ja0 and ja1can be set to appropriate combination to select the different fifo sizes or to disable the jitter attenuator. in hardware mode, appropriate setting of the pins ja0 and ja1 selects the different fifo sizes or disable the jitter attenuator. data is clocked into the fifo with the associated clock signal (txclk or rxclk) and clocked out of the fifo with the dejittered t able 11: j itter a mplitude versus m odulation f requency (j itter t olerance ) b it r ate ( kb / s ) s tandard i nput j itter a mplitude (ui p - p ) m odulation f requency a1 a2 a3 f 1(h z ) f 2(h z ) f 3( k h z ) f 4( k h z ) f 5( k h z ) 34368 itu-t g.823 1.5 0.15 - 100 1000 10 800 - 44736 gr-499 core cat i 5 0.1 - 10 2.3k 60 300 - 44736 gr-499 core cat ii 10 0.3 - 10 669 22.3 300 - 51840 gr-253 core cat ii 15 1.5 0.15 10 30 300 2 20 t able 12: j itter t ransfer s pecifications e3 ds3 sts-1 etsi tbr-24 gr-499 core section 7.3.2 category i and category ii gr-253 core section 5.6.2.1
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 36 clock. when the fifo is within two bits of overflowing or underflowing, the fifo limit status bit, fl is set to 1 in the alarm status register. reading this bit clears the fifo and resets the bit into default state. n ote : it is recommended to select the 16-bit fifo for delay-sensitive applications as well as for removing smaller amounts of jitter. table 13 specifies the jitter transfer mask requirements for various data rates. the jitter attenuator within the XRT75L00 meets the latest jitter attenuation specifications and/or jitter transfer characteristics as shown in the figure 24. t able 13: j itter t ransfer p ass m asks r ate ( kbits ) m ask f1 (h z ) f2 (h z ) f3 (h z ) f4 ( k h z ) a1(db) a2(db) 34368 g.823 etsi-tbr-24 100 300 3 k 800 k 0.5 -19.5 44736 gr-499, cat i gr-499, cat ii gr-253 core 10 10 10 10k 56.6k 40 - - - 15k 300k 15k 0.1 0.1 0.1 - - - 51840 gr-253 core 10 40k - 400k 0.1 - f igure 24. j itter t ransfer r equirements and j itter a ttenuator p erformance f1 a1 f2 jitter amplitude jitter frequency (khz) a2 f3 f4
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 37 7.0 serial host interface: a flexible serial microprocessor interface is incorporated in the XRT75L00. the interface is generic and is designed to support the common microprocessors/microcontrollers. the XRT75L00 operates in host mode when the host/hw pin is tied high. the serial interface includes a serial clock (sclk), serial data input (sdi), serial data output (sdo), chip select (cs) and interrupt output (int). the serial interface timing is shown in figure 11. the active low interrupt output signal (int pin) indicates alarm conditions like los, dmo and fl to the processor. when the XRT75L00 is configured in host mode, the following input pins,txlev, taos, rlb, llb, e3, sts-1/ ds3, reqen, jatx/rx, ja0 and ja1 are disabled and must be connected to ground. table 14 below illustrates the functions of the shared pins in either host mode or in hardware mode. n ote : while configured in host mode, the txon input pin will be active if the txon bit in the control register is set to 1, and can be used to turn on and off the transmit output drivers. this permits a system designed for redundancy to quickly switch out a defective line card and switch-in the backup line card. t able 14: f unctions of shared pins p in n umber i n h ost m ode i n h ardware m ode 24 cs rxclkinv 26 sclk txclkinv 25 sdi rxon 27 sdo rxmon 28 int losmut t able 15: r egister m ap and b it n ames a ddress (h ex ) p arameter n ame d ata b its 76 5 43210 0x00 aps/redundancy (read/write) reserved reserved reserved rxon reserved reserved reserved txon 0x01 interrupt enable (read/write) reserved cnt_satie prbsie flie rlolie rlosie dmoie 0x02 interrupt status (reset on read) reserved cnt_satis prbsis flis rlolis rlosis dmois 0x03 alarm status (read only) reserved prbsls dlos alos fl rlol rlos dmo 0x04 transmit control (read/write) reserved txmon insprbs reserved taos txclkinv txlev 0x05 receive control (read/write) reserved dlosdis alosdis rxclkinv losmut rxmon reqen 0x06 block control (read/write) reserved prbsen rlb llb e3 sts1/ ds3 sr/dr 0x07 jitter attenuator (read/write) reserved pntrst ja1 jatx/rx ja0
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 38 0x08- 0x1f reserved 0x20 interrupt enable- global (read/write) reserved reserved reserved inten 0x21 interrupt status (read only) reserved reserved reserved intst 0x22- 0x2f reserved reserved 0x30 prbs error count (msb) msb lsb 0x31 prbs error count (lsb) msb lsb 0x32-0x37 reserved 0x38 prbs holding msb lsb 0x39- 0x3d reserved 0x3e chip_id (read only) device part number (7:0) 0x3f chip_version (read only) chip revision number (7:0) t able 15: r egister m ap and b it n ames a ddress (h ex ) p arameter n ame d ata b its 76 5 43210
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 39 t able 16: r egister m ap d escription a ddress (h ex ) t ype b it l ocation s ymbol d escription d efault v alue (b in ) 0x00 r/w d0 rxon bit 4 = rxon, receiver turn on. writing a 1 to the bit field turns on the receiver and a 0 turn off the receiver. 0 d4 txon bit 0 = txon, transmitter turn on. writing a 1 to the bit field turn on the transmitter. writing a 0 turns off the transmitter and tri-state the transmitter output (ttip/tring). 0 0x01 r/w d0 dmoie writing a 1 to this bit field enables the dmo inter- rupt and triggers an interrupt when the transmitter driver fails. writing a 0 disables the interrupt. 0 d1 rlosie writing a 1 to this bit field enables the rlos inter- rupt and triggers an interrupt when the rlos condi- tion occurs. writing a 0 disables the interrupt. 0 d2 rlolie writing a 1 to this bit field enables the rlol inter- rupt and triggers an interrupt when rlol condition occurs. writing a 0 disables the interrupt. 0 d3 flie writing a 1 to this bit field enables the fl interrupt and triggers an interrupt when the fifo limit of the jitter attenuator is within 2 bits of overflow/underflow condition. writing a 0 disables the interrupt. n ote : this bit field is ignored when the jitter attenuator is disabled. 0 d4 prbsie writing a 1 to this bit enables the prbs bit error interrupt. 0 d5 cnt_satie writing a 1 to this bit enables the prbs error- counter saturation interrupt. when the prbs error counter reaches 0xffff, an interrupt will be gener- ated. 0
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 40 0x02 reset upon read d0 dmois this bit is set to 1 every time a dmo status change has occurred since the last cleared interrupt.this bit is cleared when read. 0 d1 rlosis this bit is set to 1 every time a rlos status change has occurred since the last cleared interrupt. this bit is cleared when read. 0 d2 rlolis this bit is set to 1 every time a rlol status change has occurred since the last cleared interrupt. this bit is cleared when read. 0 d3 flis this bit is set to 1 every time a fifo limit status change has occurred since the last cleared interrupt. this bit is cleared when read. 0 d4 prbsis this bit is set to 1 when a prbs bit error is detected. this bit is cleared when read. 0 d5 cnt_satis this bit is set to 1 when the prbs error counter has saturated (0xffff). this bit is cleared when read. 0 0x03 read only d0 dmo this bit is set to 1 every time the mtip/mring input pins have not detected any bipolar pulses for 128 consecutive bit periods. 0 d1 rlos this bit is set to 1 every time the receiver declares an los condition. 0 d2 rlol this bit is set to 1 every time when the receiver declares a loss of lock condition. 0 d3 fl this bit is set to 1 every time the fifo in the jitter attenuator is within 2 bit of underflow/overflow condi- tion. 0 d4 alos this bit is set to 1 every time the receiver declares analog los condition. 0 d5 dlos this bit is set to 1 every time the receiver declares digital los condition. 0 d6 prbsls this bit is set to 1 every time the prbs detects a bit error. 0 t able 16: r egister m ap d escription a ddress (h ex ) t ype b it l ocation s ymbol d escription d efault v alue (b in )
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 41 0x04 r/w d0 txlev writing a 1 to this bit disables the transmit build-out circuit and writing a 0 enables the transmit build-out circuit. n ote : see section 4.03 for detailed description. 0 d1 txclkinv writing a 1 to this bit configures the transmitter to sample the data on tpdata/tndata input pins on the rising edge of txclk. 0 d2 taos setting this bit to 1 causes a continuous stream of marks to be sent out at the ttip and tring pins. 0 d3 reserved this bit location is not used. d4 insprbs writing a 1 to this bit causes the prbs generator to insert a single-bit error onto the transmit prbs data stream. n ote : prbs generator/detector must be enabled for this bit to have any effect. 0 d5 txmon when this bit is set to 1, the driver monitor is con- nected to its own transmit channel and monitors the transmit driver. when a transmit failure is detected, the dmo output will go high. when this bit is 0, mtip and mring can be con- nected to other transmit channel for monitoring. 0 0x05 r/w d0 reqen setting this bit to 1 enables the receive equalizer . n ote : see section 2.01 for detailed description. 0 d1 rxmon writing a 1 to this bit configures the receiver into monitoring mode. in this mode, the receiver can monitor a signal at the rtip/rring pins that be atten- uated up to 20db flat loss. 0 d2 losmut writing a 1 to this bit causes the rpos/rneg out- puts to be grounded while the los condition is declared. n ote : if this bit has ben set, it will remain set evan after los condition is cleared. 0 d3 rxclkinv writing a 1 to this bit configures the receiver to out- put rpos/rneg data on the falling edge of rxclk. 0 d4 alosdis writing a 1 to this bit disables the alos detector. 0 d5 dlosdis writing a 1 to this bit disables the dlos detector. 0 t able 16: r egister m ap d escription a ddress (h ex ) t ype b it l ocation s ymbol d escription d efault v alue (b in )
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 42 0x06 r/w d0 sr/dr writing a 1 to this bit configures the receiver and transmitter into single-rail (nrz) mode. 0 d1 sts-1/ds3 writing a 1 to this bit configures the channel 0 into sts-1 mode. n ote : this bit field is ignored if the chip is configured to operate in e3 mode. 0 d2 e3 writing a 1 to this bit configures the chip in e3 mode. 0 d3 llb writing a 1 to this bit configures the chip in local loopback mode. 0 d4 rlb writing a 1 to this bit configures the chip in remote loopback mode. 0 d5 prbsen writing a 1 to this bit enables the prbs generator/ detector.prbs generator generate and detect either 2 15 -1 (ds3 or sts-1) or 2 23 -1 (for e3). the pattern generated and detected are unframed pattern. 0 0x07 r/w d0 ja0 this bit along with ja1 bit configures the jitter attenu- ator as shown in the table below. 0 d1 jatx/rx writing a 1 to this bit selects the jitter attenuator in the transmit path. a 0 selects in the receive path. 0 d2 ja1 this bit along with the ja0 configures the jitter atten- uator as shown in the table. 0 d3 pntrst setting this bit to 1 resets the read and write point- ers of the jitter attenuator fifo. 0 t able 16: r egister m ap d escription a ddress (h ex ) t ype b it l ocation s ymbol d escription d efault v alue (b in ) rlb 0 0 loopback mode normal operation analog local llb 0 1 1 1 remote digital 0 1 ja0 0 0 mode 16 bit fifo 32 bit fifo ja1 0 1 1 1 disable jitter attenuator 0 1 disable jitter attenuator
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 43 t able 17: r egister m ap d escription - g lobal 0x08 reserved a ddress (h ex ) t ype b it l ocation s ymbol d escription d efault v alue (b in ) 0x20 r/w d0 inten bit 0 = inten writing a 1 to this bit enables the interrupts. 0 0x21 read only d0 intst bit 0 = intst bit is set to 1 if an interrupt service is required. the source level interrupt status register is read to determine the cause of interrupt. 0 0x22 - 0x2f reserved 0x30 reset upon read d[7:0] prbsmsb prbs error counter msb [15:8] 0x31 reset upon read d[7:0] prbslsb prbs error counter lsb [7:0] 0x32- 0x37 reserved 0x38 read only d[7:0] prbshold prbs holding register 0x39- 0x3d reserved 0x3e read only d[7:0] chip_id this read only register contains device id. 01110001 0x3f read only d[7:0] chip_version this read only register contains chip version number 00000001 t able 16: r egister m ap d escription a ddress (h ex ) t ype b it l ocation s ymbol d escription d efault v alue (b in )
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 44 8.0 diagnostic features: 8.1 prbs generator and detector: the XRT75L00 contains an on-chip pseudo random binary sequence (prbs) generator and detector for diagnostic purpose. this feature is only available in host mode. with the prbsen bit = 1, the transmitter will send out prbs of 2 23 -1 in e3 rate or 2 15 -1 in sts-1/ds3 rate. at the same time, the receiver prbs detector is also enabled. when the correct prbs pattern is detected by the receiver, the rneg/lcv pin will go low to indicate prbs synchronization has been achieved. when the prbs detector is not in sync the prbsls bit will be set to 1 and rneg/lcv pin will go high. with the prbs mode enabled, the user can also insert a single bit error by toggling insprbs bit. this is done by writing a 1 to insprbs bit. the receiver at rneg/lcv pin will pulse high for half rxclk cycle for every bit error detected. any subsequent single bit error insertion must be done by first writing a 0 to insprbs bit and followed by a 1. when prbs mode is enabled, the prbs counter starts counting each single bit error. the prbs counter is 16 bits wide. the current value in the counter can be read via two readback operations of the serial i/o registers. 1) either the least significant byte (lsb, address 0x30) or the most significant byte (msb, address 0x31) can be read first. the value of the un-read register will be copied into the holding register (address 0x38) and both the lsb and msb registers will be reset to zero. 2) read the holding register and concatenate the result with the value from the first read operation to get the full 16 bit counter value. when the prbs mode is first enabled, errors will be counted while the receiver logic is synchronizing to the prbs pattern. when rneg/lcv goes low indicating prbs synchronization, reset the counter by reading either the lsb or the msb register. figure 25 shows the status of rneg/lcv pin when the XRT75L00 is configured in prbs mode. 8.2 loopbacks: the XRT75L00 offers three loopback modes for diagnostic purposes. in hardware mode, the loopback modes are selected via the rlb and llb pins. in host mode, the rlb and llb bits in the control registers select the loopback modes. 8.2.1 analog loopback: in this mode, the transmitter outputs (ttip and tring) are connected internally to the receiver inputs (rtip and rring) as shown in figure 26. data and clock are output at rclk, rpos and rneg pins for the corresponding transceiver. analog loopback exercises most of the functional blocks of the device including the jitter attenuator which can be selected in either the transmit or receive path. XRT75L00 can be configured in analog loopback either in hardware mode via the llb and rlb pins or in host mode via llb and rlb bits in the channel control registers. f igure 25. prbs mode rclk rneg/lcv sync loss prbs sync single bit error
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 45 n otes : 1. in the analog loopback mode, data is also output via ttip and tring pins. 2. signals on the rtip and rring pins are ignored during analog loopback. 8.2.2 digital loopback: the digital loopback function is available either in hardware mode or host mode. when the digital loopback is selected, the transmit clock (txclk) and transmit data inputs (tpdata & tndata) are looped back and output onto the rxclk, rpos and rneg pins as shown in figure 27. the data presented on txclk, tpdata and tndata are not output on the ttip and tring pins.this provides the capability to configure the protection card (in redundancy applications) in digital loopback mode without affecting the traffic on the primary card. n ote : signals on the rtip and rring pins are ignored during digital loopback. f igure 26. a nalog l oopback f igure 27. d igital l oopback tring ttip rring rtip rpos rneg rclk tndata tclk tpdata hdb3/b3zs 1 encoder hdb3/b3zs 1 decoder jitter 2 attenuator jitter 2 attenuator timing control data & clock recovery 1 if enabled 2 if enabled and selected in either receive or transmit path tx rx tring ttip rring rtip rpos rneg rclk tndata tclk tpdata hdb3/b3zs 1 encoder hdb3/b3zs 1 decoder jitter 2 attenuator jitter 2 attenuator timing control data & clock recovery 1 if enabled 2 if enabled and selected in either receive or transmit path tx rx
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 46 8.2.3 remote loopback: with remote loopback activated as shown in figure 28,the receive data on rtip and rring is looped back after the jitter attenuator (if selected in receive or transmit path) to the transmit path using rxclk as transmit timing. the receive data is also output via the rpos and rneg pins. during the remote loopback mode, if the jitter attenuator is selected in the transmit path, the receive data after the clock and data recovery block is looped back to the transmit path and pass through the jitter attenuator using rxclk as the transmit timing. n ote : input signals on txclk, tpdata and tndata are ignored during remote loopback. 8.3 transmit all ones (taos): transmit all ones (taos) can be set either in hardware mode by pulling the taos pins high or in host mode by setting the taos control bits to 1 in the channel control registers. when the taos is set, the transmit section generates and transmits a continuous ami all 1s pattern on ttip and tring pins. the frequency of this 1s pattern is determined by tclk.taos data path is shown in figure 29. f igure 28. r emote l oopback f igure 29. t ransmit a ll o nes (taos) tring ttip rring rtip rpos rneg rclk tndata tclk tpdata hdb3/b3zs 1 encoder hdb3/b3zs 1 decoder jitter 2 attenuator jitter 2 attenuator timing control data & clock recovery 1 if enabled 2 if enabled and selected in either receive or transmit path tx rx tring ttip rring rtip rpos rneg rclk tndata tclk tpdata hdb3/b3zs encoder hdb3/b3zs decoder jitter 2 attenuator jitter 2 attenuator timing control data & clock recovery 1 if enabled 2 if enabled and selected in either receive or transmit path tx rx taos transmit all 1 1 1
XRT75L00 rev. 1.0.2 e3/ds3/sts-1 line interface unit with jitter attenuator 47 ordering information package dimensions p art n o .p ackage o perating t emperature r ange XRT75L00iv 52 pin tqfp (10mm x 10mm) -40c to +85c symbol min max min max a 0.055 0.063 1.40 1.60 a1 0.002 0.006 0.05 0.15 a2 0.053 0.057 1.35 1.45 b 0.009 0.015 0.22 0.38 c 0.004 0.008 0.09 0.20 d 0.465 0.480 11.80 12.20 d1 0.390 0.398 9.90 10.10 e 0.0256 bsc 0.65 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7 b aaa - 0.003 - 0.08 7 typ 7 typ inches millimeters note: the control dimension is the millimeter column 39 27 26 14 113 40 52 d d 1 d d 1 b e a a 2 a 1 a seating plane l c
XRT75L00 e3/ds3/sts-1 line interface unit with jitter attenuator rev. 1.0.2 48 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2004 exar corporation datasheet february 2004. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history 1.0.1 removed evaluation schematic. 1.0.2 changed the device id to reflect the correct value.

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